The present invention relates to a semiconductor memory apparatus, and more particularly, to a data output device for controlling data output operation.
Semiconductor memory apparatuses are being used in most electronic products. For example, semiconductor memory apparatuses are being used in numerous electronic products such as personal computers, televisions, audio sets and communication terminals. In use, semiconductor memory apparatuses receive and store data from different electronic elements or appliances, provide the stored data to different electronic elements or appliances upon request, etc. Accordingly, the semiconductor memory apparatuses require circuits or devices associated with the input and output of data between the different electronic elements or appliances and the semiconductor memory apparatuses. That is to say, the semiconductor memory apparatuses require circuits or devices for transmitting and receiving data to and from the different electronic elements or appliances.
FIG. 1 is a circuit diagram illustrating a conventional data output device of a semiconductor memory apparatus.
Referring to FIG. 1, a conventional data output device includes pre-driving elements and driving elements having a predetermined size. That is to say, inverters 1 and 3 are connected to a signal input terminal DRVH as pre-driving elements, and PMOS transistors 21 and 23 are connected to the respective inverters 1 and 3 as driving elements. The PMOS transistors 21 and 23 have gate terminals which are connected to the output terminals of the inverters 1 and 3, source terminals through which a supply voltage (VDD) is provided, and drain terminals which are connected to an output terminal DQ.
Also, buffers 31 and 33 are connected to a signal input terminal DRVL as pre-driving elements, and NMOS transistors 41 and 42 are connected to the respective buffers 31 and 33 as driving elements. The NMOS transistors 41 and 42 have gate terminals which are connected to the output terminals of the buffers 31 and 33, source terminals which are connected to ground, and drain terminals which are connected to the output terminal DQ.
In the conventional data output device of a semiconductor memory apparatus configured as described above, when an input signal DRVH has a high level, the high signal is inverted by the inverters 1 and 3, and low signals are applied to the gate terminals of the respective PMOS transistors 21 and 23, by which the PMOS transistors 21 and 23 are turned on. As the PMOS transistors 21 and 23 are turned on, a supply voltage is supplied to the output terminal DQ, and a high signal is outputted from the output terminal DQ.
Conversely, when an input signal DRVL has a high level, high signals are applied to the gate terminals of the respective NMOS transistors 41 and 42 by the buffers 31 and 33, by which the NMOS transistors 41 and 42 are turned on. As the NMOS transistors 41 and 42 are turned on, a current path is formed from the output terminal DQ to the ground source, and a low signal is outputted from the output terminal DQ.
The conventional data output device of a semiconductor memory apparatus, which operates as described above, has problems as follows. In general, if the slew rate of an output data signal is small, a better performance is obtained in terms of an EMI (electromagnetic interference). However, if the slew rate of the output data signal is decreased by changing the size of the pre-driving elements or the driving elements so as to decrease an EMI level, data valid window (tDV) is reduced. Furthermore, in the case where an operation frequency is increased, the degradation of tDV becomes significant.